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| CXG1178K Power Amplifier Module for JCDMA Description The CXG1178K is the power amplifier module which operates at a single power supply. This IC is designed using the Sony's original p-Gate HFET process. Features * Single power supply operation: VDD1 = VDD2 = 3.5V (High mode), 1.5V (Mid mode), 1.0V (Low mode), VGG = 2.8V * Ultrasmall package: 0.027cc (4.5mm x 4.5mm x 1.35mm) * High efficiency: add = 40.5%@POUT = 27.5dBm (High mode), add = 17.6%@POUT = 14dBm (Mid mode) * Output power (High/Mid/Low mode switching supported): POUT = 18 to 27.5dBm: High mode, POUT = 14 to 18dBm: Mid mode, POUT 14dBm: Low mode * Gain (High mode): Gp = 28.5dB (@900MHz) Applications Power amplifier for JCDMA system cellular phones Structure p-Gate HFET module Absolute Maximum Ratings * Operating case temperature * Storage temperature * Bias voltage * Bias voltage * Input power (Ta = 25C) Tcase -30 to +110 C Tstg -30 to +125 C VDD1, VDD2 6 V VGG 3.3 V (@VDD1 = VDD2 3.5V) PIN 8 dBm 8 pin LCC (Ceramic) Recommended Bias Voltage Conditions * VDD1 = VDD2 = 1.0 to 4.2V * VGG = 2.8V 1% Descriptions in this specification are specified for the Sony's recommended evaluation board . GaAs module is ESD sensitive devices. Special handling precautions are required. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E04660-PS CXG1178K Package Outline/Pin Configuration Front GND 8 PIN 1 7 VGG VDD1 2 6 GND VDD2 3 5 POUT 4 GND Back GND 8 VGG 7 1 PIN GND 6 9 GND 2 VDD1 POUT 5 3 VDD2 4 GND Note) Pin 4, 8 and 9 should be soldered on the land of the board. For the land to which Pin 9 is connected, make the through holes in the land and form the GND pattern. -2- CXG1178K Electrical Characteristics Item Frequency Current consumption 1 Current consumption 2 Current consumption 3 Gain 1 Gain 2 Gain 3 ACPR1 (High mode) ACPR2 (High mode) ACPR1 (Mid mode) ACPR2 (Mid mode) ACPR1 (Low mode) ACPR2 (Low mode) 2nd harmonics 3rd harmonics Gate current Idle current 1 Idle current 2 Idle current 3 Conditions (ZS = ZL = 50, IS-95 Modulation, Ta = 25C) Min. 887 POUT = 27.5dBm, VDD1 = VDD2 = 3.5V, VGG = 2.8V POUT = 14dBm, VDD1 = VDD2 = 1.5V, VGG = 2.8V POUT = 9dBm, VDD1 = VDD2 = 1.0V, VGG = 2.8V POUT = 27.5dBm, VDD1 = VDD2 = 3.5V, VGG = 2.8V POUT = 18dBm, VDD1 = VDD2 = 1.5V, VGG = 2.8V POUT = 14dBm, VDD1 = VDD2 = 1.0V, VGG = 2.8V POUT = 27.5dBm, VDD1 = VDD2 = 3.5V, VGG = 2.8V, 900kHz offset, 30kHz band width POUT = 27.5dBm, VDD1 = VDD2 = 3.5V, VGG = 2.8V, 1.98MHz offset, 30kHz band width POUT = 18dBm, VDD1 = VDD2 = 1.5V, VGG = 2.8V, 900kHz offset, 30kHz band width POUT = 18dBm, VDD1 = VDD2 = 1.5V, VGG = 2.8V, 1.98MHz offset, 30kHz band width POUT = 14dBm, VDD1 = VDD2 = 1.0V, VGG = 2.8V, 900kHz offset, 30kHz band width POUT = 14dBm, VDD1 = VDD2 = 1.0V, VGG = 2.8V, 1.98MHz offset, 30kHz band width POUT = 27.5dBm, VDD1 = VDD2 = 3.5V, VGG = 2.8V POUT = 27.5dBm, VDD1 = VDD2 = 3.5V, VGG = 2.8V POUT 27.5dBm, VGG = 2.8V PIN, POUT = None, VDD1 = VDD2 = 3.5V, VGG = 2.8V PIN, POUT = None, VDD1 = VDD2 = 1.5V, VGG = 2.8V PIN, POUT = None, VDD1 = VDD2 = 1.0V, VGG = 2.8V 26.5 20.5 17.5 397 95 59 28.5 22.5 19.5 -52 -62 -55 -62 -54 -63 -41 -57 1.8 85 51 40 -47 -57 -47 -57 -47 -57 -30 -30 2.5 110 66 52 Typ. Max. 925 412 102 66 Unit MHz mA mA mA dB dB dB dBc dBc dBc dBc dBc dBc dBc dBc mA mA mA mA -3- CXG1178K Recommended External Circuit C1: 1F C2: 10F GND PIN C1 VDD1 C2 C1 GND VDD2 C2 C1 GND C2 VGG POUT GND Recommended Evaluation Board Board material: Glass fabric-base epoxy Size: 40mm x 50mm x 0.6mm Relative dielectric constant: 4.6 Front VGG GND C2 Back PIN C1 POUT C2 VDD1 C1 C1 C2 VDD2 GND -4- CXG1178K Example of Representative Characteristics Conditions: f = 900MHz VDD1 = VDD2 = 3.5V, VGG = 2.8V (High mode) VDD1 = VDD2 = 1.5V, VGG = 2.8V (Mid mode) Ta = 25C POUT vs. PIN 32 30 VDD = 3.5V 28 VDD = 1.5V 26 24 22 20 18 16 14 12 10 8 6 4 2 -26 -24 -22 -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 2 4 PIN [dBm] 600 550 500 450 400 IDD [mA] IDD vs. POUT VDD = 3.5V VDD = 1.5V POUT [dBm] 350 300 250 200 150 100 50 0 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 POUT [dBm] ACPR1 vs. POUT -36 -38 -40 -42 -44 -46 -48 -50 -52 -54 -56 -58 -60 -62 -64 -66 -68 -70 -72 -74 -54 VDD = 3.5V VDD = 1.5V -56 -58 -60 -62 ACPR2 [dBc] ACPR2 vs. POUT VDD = 3.5V VDD = 1.5V ACPR1 [dBc] -64 -66 -68 -70 -72 -74 -76 -78 -80 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 POUT [dBm] 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 POUT [dBm] -5- CXG1178K Package Outline Unit: mm 8PIN LCC 4.50 0.3 4.3 SOLDERING POINT 1.37 0.13 0.2 S X + 0.5 4.50 - 0.3 4.34 PIN 1 INDEX S DETAIL X 4 - R0.2 3.3 4 5 0.7 0.15 3 2 1 8 1.95 0.6 0.15 7 2.5 3.2 6 1.25 PACKAGE STRUCTURE NOTE: Dimension "" does not include cutting burr. SONY CODE EIAJ CODE JEDEC CODE LCC-8C-371 PACKAGE MATERIAL TERMINAL TREATMENT TERMINAL MATERIAL PACKAGE MASS CERAMIC SUBSTRATE GOLD PLATING NICKEL PLATING 0.08g -6- Sony Corporation 0.05 S |
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